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AN-1006
CYPRESS USB INTERFACE
The Cypress USB interface is the core of the system, including
all of the necessary functionality to convert USB commands
into corresponding I 2 C or SPI read/write transfers, and acts as a
FIFO to route data between the host PC and the target device.
CRYSTAL OSCILLATOR SCHEMATIC
The Cypress USB interface is its own clock master, and the board
includes a crystal oscillator circuit with a 24 MHz piezoelectric
crystal resonator to provide stability to the oscillator circuit.
The crystal resonator is driven in parallel by the XTALOUT
and XTALIN pins of the Cypress USB interface.
Application Note
24.000MHz
Y1
Figure 20. Crystal Oscillator Schematic
3DD3V
IOVDD
1DD8V
IOVDD
Local to 68053
C9
0.10uF
C10
0.10uF
C12
0.10uF
+
C15
15uF
C4
0.10uF
C5
0.10uF
IOVDD
U3
10k0
R1
10k0
R2
3G SCL
1B RDY0/SLRD
7G CTL0/FLAGA
2G CLKOUT
WAKEUP
RESET
PA0/INT0
PA1/INT1
PA2/SLOE
PA3/WU2
PA4/FIFOADR0
PA5/FIFOADR1
PA6/PKTEND
PA7/FLAGD/SLCS
4F
4H
4G
5H
5G
5F
6H
6B
6A
3B
PD4/FD[12] 3A
3C
24.000MHz
Y1
DPLUS
DMINUS
SCL
SDA
USB_CLK
IOVDD
R5
R15
49R9
2E DPLUS
1E DMINUS
3F
SDA
1A
RDY1/SLWR
7H
8H CTL1/FLAGB
CTL2/FLAGC
2B
IFCLK
2C XTALOUT
1C XTALIN
7B
8B
8G
6G
8F
7F
6F
8C
7C
6C
3H
PB0/FD[0]
PB1/FD[1]
PB2/FD[2]
PB3/FD[3]
PB4/FD[4]
PB5/FD[5]
PB6/FD[6]
PB7/FD[7]
8A
PD0/FD[8] 7A
PD1/FD[9]
PD2/FD[10]
PD3/FD[11]
PD5/FD[13]
PD6/FD[14] 2A
PD7/FD[15]
CDATA
COUT
CLATCH2
CLATCH3
CLATCH4
CLATCH5
CCLK
R6 475R
USB_PWR_ON
CLATCH1
BRD_RESET
3V3DD
100k
C1
1.0uF
CYPRESS_CY7C68053_56BAXI
GND
IOVDD
3V3DD
2
A
Y
4
IOVDD
3V3DD
IOVDD
U4
FXLP34P5X
3V3DD
C6
0.10uF
C8
0.10uF
2
A
Y
4
U5
IOVDD
2
A
Y
FXLP34P5X
3V3DD
4
U6
FXLP34P5X
Figure 21. Cypress USB Interface Schematic
Rev. A | Page 8 of 16
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